An non-volatile memory cell, memory cell array and device
A non-volatile memory cell based on a soft breakdown mechanism is provided. The memory comprises a resistor coupled serially to a gate or source/drain region of a MOS device. When a soft breakdown occurs to the MOS device, leakage current flowing through the gate dielectric increases. The change of...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | A non-volatile memory cell based on a soft breakdown mechanism is provided. The memory comprises a resistor coupled serially to a gate or source/drain region of a MOS device. When a soft breakdown occurs to the MOS device, leakage current flowing through the gate dielectric increases. The change of the leakage current is used to indicate different states. |
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