Data erasing method, and memory apparatus having data erasing circuit using such method

The present invention is to propose a data erasing method, a memory apparatus, and a data erasing circuit which are able to reduce the time required to boost the potential of the semiconductor substrate thereby to reduce the time required to erase data. Namely, the present invention discloses a memory apparatus having a data erasing circuit that erases the stored data by applying an erasing voltage between a semiconductor substrate and a control gate so as to discharge the electric charges accumulated in a floating gate. In this case, the data erasing circuit boosts the potential of the semiconductor substrate side while placing the control gate into its floating state; and applies an erasing voltage between the semiconductor substrate and the control gate so that the potential of the control gate is at a predetermined potential.