Clock control circuit

A clock signal is supplied from a clock oscillator to a gate circuit. In a period in which a reset signal is at the ""H"" level, the clock signal is supplied to an internal circuit. When the reset signal becomes at the ""L"" level, a control is performed by a gate control circuit so as to stop the supply of the clock signal. Consequently, even when a delay signal in the internal circuit becomes longer than one cycle of the clock signal, occurrence of an erroneous operation can be prevented.