Built-in spare row and column replacement analysis system for embedded memories

A built-in replacement analysis (BIRA) circuit allocates spare rows and columns of cells for replacing rows and columns of an array of memory cells in response to an input sequence of cell addresses, each identifying a row address and a column address of each defective cell of the cell array. The BIRA subsystem, including a row register corresponding each spare row and a column register corresponding to each spare column, responds to incoming cell addresses by writing their included row address into the row registers, by writing their column addresses into the column registers, and by writing link bits into the column registers. Each link bit links a row and a column register by storing row and column addresses of a defective cell. The BIRA subsystem also writes a ""multiple cell"" bit into each row register to indicate when the row address it stores includes more than one defective cell. The row and column addresses stored in these registers indicate the array rows and columns for which spare rows and columns are to be allocated. Each row and column register also includes a ""permanent"" bit the BIRA subsystem sets to indicate when the spare row or column allocation indicated by its stored row or column address is permanent. The BIRA subsystem efficiently allocates spare row and columns by manipulating the data stored in the row and column registers in response to a sequence of defective cell address.