Improving the triggering of an ESD NMOS through the use of an n-type buried layer

An ESD NMOS structure with an odd number of N-type structures built into a P-type well. Buried N-type structures are positioned between the N-type structures. The center N-type structure and each alternate N-type structure are electrically connected to each other, to the buried N-type structures, and to the output contact; while the other N-type structures are electrically connected to each other and the P-well and to ground. When a positive ESD event occurs, a depletion zone is created in the P-well between the N-type buried structures and the N-type structures thereby increasing the resistivity of the structure. Moreover, when a positive ESD event occurs, the lateral NPN transistors on either side of the center N-type structure break down and snap back. The resulting current travels through the area of increased resistivity and thereby creates a larger voltage along the P-well from the center N-type structure out toward the distal N-type structures. The combination of the increased resistivity and the higher voltage act in combination to lower the triggering voltage of the ESD structure.