Method for manufacturing bit line contact structure of semiconductor memory

A method is disclosed for manufacturing bit line contact structures of semiconductor memories. The manufacturing method comprises the steps of providing a semiconductor substrate, forming a plurality of gates on the surface of said substrate, applying a first insulating layer to cover said surface of said substrate and said gates, selectively forming a plurality of gate contact windows at the locations of said gates, selectively forming bit line contact windows in said first insulating layer, said bit line contact windows contacting said substrate, and filling said gate contact windows and said bit line contact windows with a conducting layer.