A semiconductor device

The purpose of the aligner of the present invention is to provide a flip chip BGA which can exhibit a high-speed electric transmission characteristic while minimizing the formation of voids in a sealing resin filled between a semiconductor chip and a wiring board. In a silicon chip 1A having a flip...

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Hauptverfasser: USAMI, MASAMI, KATAGIRI, MITSUAKI, UJIIE, KENJI
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creator USAMI, MASAMI
KATAGIRI, MITSUAKI
UJIIE, KENJI
description The purpose of the aligner of the present invention is to provide a flip chip BGA which can exhibit a high-speed electric transmission characteristic while minimizing the formation of voids in a sealing resin filled between a semiconductor chip and a wiring board. In a silicon chip 1A having a flip chip mounted on a package board, a power supply circuit, an input/output circuit and a plurality of bonding pads BP are positioned in the central area of the major surface thereof; and solder bumps 6 electrically connected to the bonding pads BP via Cu wiring 10 are positioned in the form of a matrix in the area of the major surface other than the central area. One (VDDQ) of the solder bumps 6 for input/output power and one (DQ) of the solder bumps 6 for data signal input/output are positioned in a first area adjacent to the central area, and one (ADR) of the bumps 6 for address signal input are positioned in a second area outside the first area.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_TWI222185BB</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>TWI222185BB</sourcerecordid><originalsourceid>FETCH-epo_espacenet_TWI222185BB3</originalsourceid><addsrcrecordid>eNrjZBBzVChOzc1Mzs9LKU0uyS9SSEkty0xO5WFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFicmpeakl8SHhnkZGRoYWpk5OxkQoAQBi2iF_</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>A semiconductor device</title><source>esp@cenet</source><creator>USAMI, MASAMI ; KATAGIRI, MITSUAKI ; UJIIE, KENJI</creator><creatorcontrib>USAMI, MASAMI ; KATAGIRI, MITSUAKI ; UJIIE, KENJI</creatorcontrib><description>The purpose of the aligner of the present invention is to provide a flip chip BGA which can exhibit a high-speed electric transmission characteristic while minimizing the formation of voids in a sealing resin filled between a semiconductor chip and a wiring board. In a silicon chip 1A having a flip chip mounted on a package board, a power supply circuit, an input/output circuit and a plurality of bonding pads BP are positioned in the central area of the major surface thereof; and solder bumps 6 electrically connected to the bonding pads BP via Cu wiring 10 are positioned in the form of a matrix in the area of the major surface other than the central area. One (VDDQ) of the solder bumps 6 for input/output power and one (DQ) of the solder bumps 6 for data signal input/output are positioned in a first area adjacent to the central area, and one (ADR) of the bumps 6 for address signal input are positioned in a second area outside the first area.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2004</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20041011&amp;DB=EPODOC&amp;CC=TW&amp;NR=I222185B$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20041011&amp;DB=EPODOC&amp;CC=TW&amp;NR=I222185B$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>USAMI, MASAMI</creatorcontrib><creatorcontrib>KATAGIRI, MITSUAKI</creatorcontrib><creatorcontrib>UJIIE, KENJI</creatorcontrib><title>A semiconductor device</title><description>The purpose of the aligner of the present invention is to provide a flip chip BGA which can exhibit a high-speed electric transmission characteristic while minimizing the formation of voids in a sealing resin filled between a semiconductor chip and a wiring board. In a silicon chip 1A having a flip chip mounted on a package board, a power supply circuit, an input/output circuit and a plurality of bonding pads BP are positioned in the central area of the major surface thereof; and solder bumps 6 electrically connected to the bonding pads BP via Cu wiring 10 are positioned in the form of a matrix in the area of the major surface other than the central area. One (VDDQ) of the solder bumps 6 for input/output power and one (DQ) of the solder bumps 6 for data signal input/output are positioned in a first area adjacent to the central area, and one (ADR) of the bumps 6 for address signal input are positioned in a second area outside the first area.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2004</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBBzVChOzc1Mzs9LKU0uyS9SSEkty0xO5WFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFicmpeakl8SHhnkZGRoYWpk5OxkQoAQBi2iF_</recordid><startdate>20041011</startdate><enddate>20041011</enddate><creator>USAMI, MASAMI</creator><creator>KATAGIRI, MITSUAKI</creator><creator>UJIIE, KENJI</creator><scope>EVB</scope></search><sort><creationdate>20041011</creationdate><title>A semiconductor device</title><author>USAMI, MASAMI ; KATAGIRI, MITSUAKI ; UJIIE, KENJI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_TWI222185BB3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2004</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>USAMI, MASAMI</creatorcontrib><creatorcontrib>KATAGIRI, MITSUAKI</creatorcontrib><creatorcontrib>UJIIE, KENJI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>USAMI, MASAMI</au><au>KATAGIRI, MITSUAKI</au><au>UJIIE, KENJI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>A semiconductor device</title><date>2004-10-11</date><risdate>2004</risdate><abstract>The purpose of the aligner of the present invention is to provide a flip chip BGA which can exhibit a high-speed electric transmission characteristic while minimizing the formation of voids in a sealing resin filled between a semiconductor chip and a wiring board. In a silicon chip 1A having a flip chip mounted on a package board, a power supply circuit, an input/output circuit and a plurality of bonding pads BP are positioned in the central area of the major surface thereof; and solder bumps 6 electrically connected to the bonding pads BP via Cu wiring 10 are positioned in the form of a matrix in the area of the major surface other than the central area. One (VDDQ) of the solder bumps 6 for input/output power and one (DQ) of the solder bumps 6 for data signal input/output are positioned in a first area adjacent to the central area, and one (ADR) of the bumps 6 for address signal input are positioned in a second area outside the first area.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title A semiconductor device
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-23T19%3A26%3A05IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=USAMI,%20MASAMI&rft.date=2004-10-11&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ETWI222185BB%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true