A semiconductor device

The purpose of the aligner of the present invention is to provide a flip chip BGA which can exhibit a high-speed electric transmission characteristic while minimizing the formation of voids in a sealing resin filled between a semiconductor chip and a wiring board. In a silicon chip 1A having a flip chip mounted on a package board, a power supply circuit, an input/output circuit and a plurality of bonding pads BP are positioned in the central area of the major surface thereof; and solder bumps 6 electrically connected to the bonding pads BP via Cu wiring 10 are positioned in the form of a matrix in the area of the major surface other than the central area. One (VDDQ) of the solder bumps 6 for input/output power and one (DQ) of the solder bumps 6 for data signal input/output are positioned in a first area adjacent to the central area, and one (ADR) of the bumps 6 for address signal input are positioned in a second area outside the first area.