Semiconductor integrated circuit

The scale of a function selector circuit is reduced by providing a controller which can change both the rise and fall characteristics of a signal waveform outputted from an output buffer (43) and the logic threshold value in an input buffer (40, 41) in accordance with the logic level of a common node signal fed optionally, so that both the rise and fall characteristics of a signal waveform outputted from an output buffer (43) and the logic threshold value in an input buffer can be changed, thereby the scale of the functional selection circuit can be reduced. A coupling circuit includes a first transistor of depletion type to lower the voltage level of a signal inputted to a second circuit, so as to prevent a potential with reverse polarity to the one conducting the channel between the gate and drain of the transistor, and thereby reduce the undesired current flowing through a transistor and exhibiting the GIDL characteristics. The layout of an output circuit is optimized by coupling the output buffer and the output driver through signal lines which are formed by using an upper layer where a memory cell array is formed.