Ferroelectric random access memory
Disclosed is a ferroelectric random access memory including a plurality of bit lines extending in one direction, a plurality of word lines extending in another direction perpendicular to the one direction, and a plurality of unit cells arranged in an MxN array while being connected to associated one...
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Sprache: | eng |
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Zusammenfassung: | Disclosed is a ferroelectric random access memory including a plurality of bit lines extending in one direction, a plurality of word lines extending in another direction perpendicular to the one direction, and a plurality of unit cells arranged in an MxN array while being connected to associated ones of the lines, each of the unit cells consisting of one transistor and one capacitor. The unit cells are grouped into a plurality of unit cell groups, each of the unit cell groups consisting of a plurality of unit cells connected to associated ones of the bit lines, respectively, in such a fashion that they are arranged in an interlaced fashion in a row direction or in a column direction, those of the bit lines connected to each of the bit lines being connected together in series. The memory includes a dummy cell group consisting of a plurality of dummy cells each connected to an associated one of the bit lines at an optional position on the associated bit line, each of the dummy cells consisting of one transistor and one capacitor, a first switching transistor group consisting of a plurality of switching transistors each serving to switch a connection among associated ones of the unit cells on one of the bit lines corresponding to an associated one of the dummy cells in response to a control signal externally applied thereto, and a second switching transistor group consisting of a plurality of switching transistors each serving to erase data stored in an associated one of the dummy cells in response to a control signal externally applied thereto. Respective capacitors of the dummy cells are made of a dielectric film having no spontaneous polarization characteristic. When data is read out from an optional one of the unit cells on a selected one of the bit lines, a predetermined voltage outputted from that of dummy cells connected to an inverted bit line neighboring to the selected bit line is provided as a reference voltage required for a comparison with a voltage corresponding to the read-out data. |
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