Memory test method, information recording medium and semiconductor integrated circuit

The purpose of the present invention is to provide a kind of method capable of testing on-chip memory with excellent efficiency. The invented method for testing memory of semiconductor integrated circuit (IC) is provided with the followings: CPU (102), which has command queue; memories (107, 108); and bus (105) for connecting CPU and memory. The test program is stored in the command queue, and the test program is executed in the CPU to access the memory through the bus. After the test program is stored in the command queue, once the test program is fetched, it is conducted repeatedly from the command queue but not from the bus. Since the same test program can be repeatedly executed by using the loop queue action of the command queue, no branching command is required. Only the test program, which is repeatedly executed, is repeatedly fetched from the command queue; and the memory read/write access for testing memory and the memory access for fetching the command do not compete on the bus. Thus, it is capable of increasing the on-chip memory test efficiency of semiconductor IC.