Direct memory access controller for converting a transfer mode flexibly in accordance with a data transfer counter value

A DMA controller of the present invention includes a burst/single mode control circuit for automatically converting a DMA transfer operation mode to a burst mode and/or a single mode regardless of a data transfer counter value, and for performing the DMA transfer operation. The burst/single mode control circuit carries out the burst mode DMA transfer operation without control operation of the CPU by the number of times corresponding to a quotient which is the result that the data transfer counter value is divided by the burst length, and carries out successively the single mode DMA transfer operation by the number of times corresponding to a remainder of the division.