Phase lock loop circuit

The present invention is related to PLL (phase lock loop) circuit, which has phase comparator 20, complete integration loop filter 21, VCO14, and loop counter 22, and is provided with a prediction window circuit 23 that outputs an HWIN (prediction window signal) for predicting the generation position of an REF and an absence compensating circuit 24, which outputs a d.REFX (the first correction signal) for correcting the absence and a d.VARX (the second correction signal) for canceling the phase difference between a VAR (comparison signal) and the d.REFX. The phase comparator 20 outputs signals Ph1 and Ph2 corresponding to the phase difference between the VAR and d.REFX and signals Ph1 and Ph2, which correspond to the phase difference between the d.REFX and d.VARX when REF is absent. By performing proper absence compensation when an REF is absent, a stable CLK (clock) is generated even VCO 14 (voltage-controlled oscillator), which has a very wide frequency variation range, is used. In addition, gate control signal Gc, which generates and makes the phase of VAR exceed one clock, is disposed. A triple-state buffer, which outputs triple-state signal based on the phase difference of REF and VAR, and is controlled to stay at an activated state according to the signal Gc, is disposed at the phase comparator. Under the condition that phase difference of REF and VAR is in the vicinity of zero, a stable clock is generated as VCO 14 having a very wide frequency variation range is used.