Method for manufacturing nonvolatile semiconductor memory with narrow variation in threshold voltages

In a method for manufacturing a memory cell of a nonvolatile semiconductor memory, a floating gate 3, first insulating film 7 and control gate 8 are successively stacked on a tunnel oxide film 2 formed on a substrate of the nonvolatile semiconductor memory. The control gate 8, the first insulating film 7 and the floating gate 3 are patterned in stripes. Subsequently, a damaged portion of the tunnel oxide film 2 immediately below a sidewall of the floating gate 3 is removed by isotropic etching. A second insulating film 10 is deposited to cover the control gate 8, sidewalls of the first insulating film 7, the floating gate 3 and the tunnel oxide film 2. Thereby, a variation in threshold voltages between memory cells is suppressed.