Damascene-gate process for the fabrication of MOSFET devices

A sub-0.1 m MOSFET device having minimum poly depletion, salicided source and drain junctions and very low sheet resistance poly-gates is provided utilizing a damascene-gate process wherein the source and drain implantation activation annealing and silicidation occurs in the presence of a dummy gate...

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Hauptverfasser: BRODSKY, STEPHEN BRUCE, HANAFI, HUSSEIN IBRAHIM, ROY, RONNEN ANDREW, BOYD, DIANE CATHERINE
Format: Patent
Sprache:eng
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Zusammenfassung:A sub-0.1 m MOSFET device having minimum poly depletion, salicided source and drain junctions and very low sheet resistance poly-gates is provided utilizing a damascene-gate process wherein the source and drain implantation activation annealing and silicidation occurs in the presence of a dummy gate region which is thereafter removed and replaced with a polysilicon gate region.