Semiconductor device

A semiconductor apparatus has an NPN (or PNP) laterally three-layered pillar formed in a mesh form among a plurality of trench type element isolation regions, and having a source and gate on an upper surface of the three-layered pillar, and a drain on a lower surface thereof. A depth DT and minimum...

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Hauptverfasser: KOUZUKI, SHIGEO, USUI, YASUNORI
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:A semiconductor apparatus has an NPN (or PNP) laterally three-layered pillar formed in a mesh form among a plurality of trench type element isolation regions, and having a source and gate on an upper surface of the three-layered pillar, and a drain on a lower surface thereof. A depth DT and minimum planar width Wtmin of the element isolation region and a width WP of the three-layered pillar are configured to satisfy a relation of 3.75 ≤ DT/WP ≤ 60 or 5.5 ≤ DT/Wtmin ≤ 14.3. The above configuration realizes a high breakdown voltage and low on-resistance.