DRAM-cells arrangement and its production method

A memory-cell has a storage-transistor (S) and a transfer-transistor (T). A gate-electrode of the transfer-transistor (T) and a control-gate-electrode of the storage-transistor (S) are connected with a word-line (W). The storage-transistor (S) has a floating-gate-electrode, which is separated from a channel-region of the storage-transistor (S) by means of a 1st dielectric and is connected with a 1st source/drain-region of the transfer-transistor (T). The control-gate-electrode is separated from the floating-gate-electrode by means of a 2nd dielectric. A 1st source/drain-region of the storage-transistor (S) is connected with a bit-line (B), which extends perpendicularly to the word-line (W). The storage-transistor (S) and the transfer-transistor (T) are preferably of different conductive type. In writing an information, the transfer-transistor (T) conducts and the storage-transistor (S) is off. In reading an information, the transfer-transistor (T) is off and the storage-transistor (S) conducts.