Integrated circuit-arrangement to test transistors and semiconductor-wafer with such circuit-arrangement

Circuit-arrangements to test transistors (T11, ..., T36) are arranged in slit-frames between integrated circuits on a semiconductor-wafer. In order to increase the number of the testable transistors in a small area- consumption, the transistors (T11, ..., T36) are arranged in a matrix form in at lea...

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Bibliographische Detailangaben

Hauptverfasser:	GUENTER, GERSTMEIER, VALENTIN, ROSSKOPF
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS SEMICONDUCTOR DEVICES STATIC STORES
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