Integrated circuit-arrangement to test transistors and semiconductor-wafer with such circuit-arrangement

Circuit-arrangements to test transistors (T11, ..., T36) are arranged in slit-frames between integrated circuits on a semiconductor-wafer. In order to increase the number of the testable transistors in a small area- consumption, the transistors (T11, ..., T36) are arranged in a matrix form in at least two rows. The drain-source paths of the transistors of the 1st row (T11, ..., T16) are connected between the terminal-pads (P11, ..., P6) and their gate-terminals are connected to a common terminal-pad (P1). The drain-source paths of the transistors (T21, ..., T26) of the 2nd row are connected on one hand to one of the terminal-pads (P11, ..., P6) and on the other hand together to the other terminal-pad (P4). Their gate-terminals are also connected to other terminal-pad (P2). The matrix-shaped arrangement of the transistors (T31, ..., T36) can be expanded with additional rows.