Semiconductor memory element
This invention relates to a semiconductor memory element with random access, it has a structure divided into memory-cells (1) and logic-region (2), said structure has a lower oxide-layer (4) arranged on a silicon-substrate (3) and an upper oxide-layer (5) arranged on the layer (4), wherein each memo...
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| creator | SCHINDLER, GUENTHER DR DEHM, CHRISTINE DR |
| description | This invention relates to a semiconductor memory element with random access, it has a structure divided into memory-cells (1) and logic-region (2), said structure has a lower oxide-layer (4) arranged on a silicon-substrate (3) and an upper oxide-layer (5) arranged on the layer (4), wherein each memory cell (1) includes at least one transistor (6) in the junction-area between the silicon-substrate (3) and the lower oxide-layer (4), and a capacitor (10) in the junction-area between the lower and upper oxide-layer (4, 5), said capacitor (10) is connected with the transistor (6) through a contact-hole (12), which is filled with metal, in the lower oxide-layer (4) and includes a ferroelectrics (12) arranged between two electrodes (11, 13), the electrode (11), which is connected with the transistor (6) and adjacent to the lower oxide-layer (4), has a larger thickness, and each logic-region (2) includes at least one transistor (15) in the junction-area between the silicon-substrate (3) and the lower oxide-layer (4), said transistor (15) is connected with the electrode on the upper side of the upper oxide-layer (5) through a contact-hole (19), which is filled with metal, in the lower and the upper oxide-layers (4, 5). According to this invention, between the capacitors (10) of the memory-cells (1) and the contact-holes (19) in the logic-region (2) is provided through filling-structures (22, 23) a level-compensation between the topology of the memory-cells (1) and the logic-region (2). |
| format | Patent |
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According to this invention, between the capacitors (10) of the memory-cells (1) and the contact-holes (19) in the logic-region (2) is provided through filling-structures (22, 23) a level-compensation between the topology of the memory-cells (1) and the logic-region (2).</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2002</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20020721&DB=EPODOC&CC=TW&NR=495970B$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20020721&DB=EPODOC&CC=TW&NR=495970B$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SCHINDLER, GUENTHER DR</creatorcontrib><creatorcontrib>DEHM, CHRISTINE DR</creatorcontrib><title>Semiconductor memory element</title><description>This invention relates to a semiconductor memory element with random access, it has a structure divided into memory-cells (1) and logic-region (2), said structure has a lower oxide-layer (4) arranged on a silicon-substrate (3) and an upper oxide-layer (5) arranged on the layer (4), wherein each memory cell (1) includes at least one transistor (6) in the junction-area between the silicon-substrate (3) and the lower oxide-layer (4), and a capacitor (10) in the junction-area between the lower and upper oxide-layer (4, 5), said capacitor (10) is connected with the transistor (6) through a contact-hole (12), which is filled with metal, in the lower oxide-layer (4) and includes a ferroelectrics (12) arranged between two electrodes (11, 13), the electrode (11), which is connected with the transistor (6) and adjacent to the lower oxide-layer (4), has a larger thickness, and each logic-region (2) includes at least one transistor (15) in the junction-area between the silicon-substrate (3) and the lower oxide-layer (4), said transistor (15) is connected with the electrode on the upper side of the upper oxide-layer (5) through a contact-hole (19), which is filled with metal, in the lower and the upper oxide-layers (4, 5). According to this invention, between the capacitors (10) of the memory-cells (1) and the contact-holes (19) in the logic-region (2) is provided through filling-structures (22, 23) a level-compensation between the topology of the memory-cells (1) and the logic-region (2).</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2002</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJAJTs3NTM7PSylNLskvUshNzc0vqlRIzUnNTc0r4WFgTUvMKU7lhdLcDPJuriHOHrqpBfnxqcUFicmpeakl8SHhJpamluYGTk7GhFUAAEpTI78</recordid><startdate>20020721</startdate><enddate>20020721</enddate><creator>SCHINDLER, GUENTHER DR</creator><creator>DEHM, CHRISTINE DR</creator><scope>EVB</scope></search><sort><creationdate>20020721</creationdate><title>Semiconductor memory element</title><author>SCHINDLER, GUENTHER DR ; DEHM, CHRISTINE DR</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_TW495970BB3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2002</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>SCHINDLER, GUENTHER DR</creatorcontrib><creatorcontrib>DEHM, CHRISTINE DR</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SCHINDLER, GUENTHER DR</au><au>DEHM, CHRISTINE DR</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor memory element</title><date>2002-07-21</date><risdate>2002</risdate><abstract>This invention relates to a semiconductor memory element with random access, it has a structure divided into memory-cells (1) and logic-region (2), said structure has a lower oxide-layer (4) arranged on a silicon-substrate (3) and an upper oxide-layer (5) arranged on the layer (4), wherein each memory cell (1) includes at least one transistor (6) in the junction-area between the silicon-substrate (3) and the lower oxide-layer (4), and a capacitor (10) in the junction-area between the lower and upper oxide-layer (4, 5), said capacitor (10) is connected with the transistor (6) through a contact-hole (12), which is filled with metal, in the lower oxide-layer (4) and includes a ferroelectrics (12) arranged between two electrodes (11, 13), the electrode (11), which is connected with the transistor (6) and adjacent to the lower oxide-layer (4), has a larger thickness, and each logic-region (2) includes at least one transistor (15) in the junction-area between the silicon-substrate (3) and the lower oxide-layer (4), said transistor (15) is connected with the electrode on the upper side of the upper oxide-layer (5) through a contact-hole (19), which is filled with metal, in the lower and the upper oxide-layers (4, 5). According to this invention, between the capacitors (10) of the memory-cells (1) and the contact-holes (19) in the logic-region (2) is provided through filling-structures (22, 23) a level-compensation between the topology of the memory-cells (1) and the logic-region (2).</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Semiconductor memory element |
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