Semiconductor memory element

This invention relates to a semiconductor memory element with random access, it has a structure divided into memory-cells (1) and logic-region (2), said structure has a lower oxide-layer (4) arranged on a silicon-substrate (3) and an upper oxide-layer (5) arranged on the layer (4), wherein each memory cell (1) includes at least one transistor (6) in the junction-area between the silicon-substrate (3) and the lower oxide-layer (4), and a capacitor (10) in the junction-area between the lower and upper oxide-layer (4, 5), said capacitor (10) is connected with the transistor (6) through a contact-hole (12), which is filled with metal, in the lower oxide-layer (4) and includes a ferroelectrics (12) arranged between two electrodes (11, 13), the electrode (11), which is connected with the transistor (6) and adjacent to the lower oxide-layer (4), has a larger thickness, and each logic-region (2) includes at least one transistor (15) in the junction-area between the silicon-substrate (3) and the lower oxide-layer (4), said transistor (15) is connected with the electrode on the upper side of the upper oxide-layer (5) through a contact-hole (19), which is filled with metal, in the lower and the upper oxide-layers (4, 5). According to this invention, between the capacitors (10) of the memory-cells (1) and the contact-holes (19) in the logic-region (2) is provided through filling-structures (22, 23) a level-compensation between the topology of the memory-cells (1) and the logic-region (2).