Chip scale package with a small surface mounting area

A chip scale package (CSP) is disclosed. The CSP includes a die with bonding pads on the perimeter of two lateral sides of active surface, a plurality of leads on the die each having first end and second end, a plurality of metal bonding wires connecting the die and the first ends of the leads, and a first sealing layer covering the active surface of the die and the metal bonding wires. Each lead has a protruding portion over the first sealing layer and located between first end and second end for the outer electrical connection. Thus the CSP has a smaller surface mounting area.