DRAM memory cell for DRAM memory device and method for manufacturing it

DRAM memory cell for a DRAM memory having: a MOSFET selection transistor which has a drain region and a source region in a semiconductor substrate column (3), a current channel which runs in the vertical direction between the drain and source regions and which can be actuated by a control gate electrode (10) being provided; a capacitor which is stacked under the MOSFET selection transistor and is electrically connected to the source region in the semiconductor substrate column (3); a metal bit line (20) which is located above the MOSFET selection transistor and is electrically connected to the drain region in the semiconductor substrate column (3), a metal word line (9) which makes electrical contact directly with the control gate electrode (10) of the MOSFET selection transistor [lacuna], the metal word line (9) extending perpendicularly with respect to the metal bit line (20) which makes electrical contact in a direct and self-aligning fashion with the drain region of the semiconductor substrate column (3).