Method of manufacturing a semiconductor device comprising a field effect transistor

Known silicide processes have the disadvantage that they may cause a short circuit between silicide contacts on source and drain regions, on the one hand, and the silicide contact on the poly gate, on the other hand, which is commonly referred to as bridging. The invention provides a simple and self-aligned method of avoiding this type of short-circuit. After the gate definition, a titled source/drain implantation (9) is carried out, while the resist mask (7) is held in place, the angle and the implantation energy being chosen such that ions impinging on the resist mask are scattered at a small angle with respect to the silicon surface. Apart from the gate, small areas (12b, 13b) are obtained thereby, which are more heavily doped than adjacent areas (12a, 13a) of the source/drain regions. Subsequently, a thermal oxide layer is grown having thicker portions (15) on top of more heavily doped regions, and thinner portions (14) on top of the more lightly doped regions. By removing the thinner oxide portions (14), spacers (15) are obtained which provide for a separation between the silicide contacts (22,23) of the source/drain regions and the silicide contact (24) of the gate. The invention provides special advantages in the field of manufacturing non-volatile memories.