SRAM generating an echo clock signal

A pipe-line processing/burst read SRAM generates an echo clock signal concurrently with the output timing of read data. The memory cell array includes a pair of memory cells storing a high level data and a low level data. The echo clock signal is generated by reading data from the pair of memory cells and alternately outputting the read data. The timing of the echo clock signal is concurrent with the output timing of read data from a data output section which reads data from a memory cell specified by a read address.