Semiconductor integrated circuit device

The present invention realizes the arrangement of a plurality of unit areas formed by one or many MOSFETs along a first direction for a specific logic circuit. There is formed a first layout extending to the first direction on the area. Along the plurality of allocated unit areas, a second layout extending to the first direction is formed outside the unit area. There is configured a layout dedicated area of the third layer extending along the second direction perpendicular to the first direction between then eighboring unit areas. A logic circuit is formed in the unit area. A neighboring layout dedicated area is combined, if necessary, to make a first connection type connect to the first layout and connect both ends of a second connection type of the third layout through the second layout.