A high voltage generation circuit in a semiconductor device
A high voltage generation circuit according to the present invention includes two PMOS transistors coupled across a PMOS transistor for a conventional high voltage generation circuit, where the two PMOS transistors being connected in series from each other to prevents a leakage current of a substrat...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | KIM, MOO-SUK |
| description | A high voltage generation circuit according to the present invention includes two PMOS transistors coupled across a PMOS transistor for a conventional high voltage generation circuit, where the two PMOS transistors being connected in series from each other to prevents a leakage current of a substrate and a latch up. A well-bias potential of the PMOS transistor for a conventional high voltage generation circuit is controlled by the two PMOS transistors. By controlling the well-bias potential of the PMOS transistor for a conventional high voltage generation circuit, a leakage current of a substrate due to potential difference of PN layers is prevented. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_TW437065BB</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>TW437065BB</sourcerecordid><originalsourceid>FETCH-epo_espacenet_TW437065BB3</originalsourceid><addsrcrecordid>eNrjZLB2VMjITM9QKMvPKUlMT1VIT81LLUosyczPU0jOLEouzSxRyMxTSFQoTs3NTM7PSylNLskvUkhJLctMTuVhYE1LzClO5YXS3Azybq4hzh66qQX58anFBYnJQMNK4kPCTYzNDcxMnZyMCasAAODgLsM</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>A high voltage generation circuit in a semiconductor device</title><source>esp@cenet</source><creator>KIM, MOO-SUK</creator><creatorcontrib>KIM, MOO-SUK</creatorcontrib><description>A high voltage generation circuit according to the present invention includes two PMOS transistors coupled across a PMOS transistor for a conventional high voltage generation circuit, where the two PMOS transistors being connected in series from each other to prevents a leakage current of a substrate and a latch up. A well-bias potential of the PMOS transistor for a conventional high voltage generation circuit is controlled by the two PMOS transistors. By controlling the well-bias potential of the PMOS transistor for a conventional high voltage generation circuit, a leakage current of a substrate due to potential difference of PN layers is prevented.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; SEMICONDUCTOR DEVICES ; STATIC STORES</subject><creationdate>2001</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20010528&DB=EPODOC&CC=TW&NR=437065B$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25544,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20010528&DB=EPODOC&CC=TW&NR=437065B$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KIM, MOO-SUK</creatorcontrib><title>A high voltage generation circuit in a semiconductor device</title><description>A high voltage generation circuit according to the present invention includes two PMOS transistors coupled across a PMOS transistor for a conventional high voltage generation circuit, where the two PMOS transistors being connected in series from each other to prevents a leakage current of a substrate and a latch up. A well-bias potential of the PMOS transistor for a conventional high voltage generation circuit is controlled by the two PMOS transistors. By controlling the well-bias potential of the PMOS transistor for a conventional high voltage generation circuit, a leakage current of a substrate due to potential difference of PN layers is prevented.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2001</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLB2VMjITM9QKMvPKUlMT1VIT81LLUosyczPU0jOLEouzSxRyMxTSFQoTs3NTM7PSylNLskvUkhJLctMTuVhYE1LzClO5YXS3Azybq4hzh66qQX58anFBYnJQMNK4kPCTYzNDcxMnZyMCasAAODgLsM</recordid><startdate>20010528</startdate><enddate>20010528</enddate><creator>KIM, MOO-SUK</creator><scope>EVB</scope></search><sort><creationdate>20010528</creationdate><title>A high voltage generation circuit in a semiconductor device</title><author>KIM, MOO-SUK</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_TW437065BB3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2001</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>KIM, MOO-SUK</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KIM, MOO-SUK</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>A high voltage generation circuit in a semiconductor device</title><date>2001-05-28</date><risdate>2001</risdate><abstract>A high voltage generation circuit according to the present invention includes two PMOS transistors coupled across a PMOS transistor for a conventional high voltage generation circuit, where the two PMOS transistors being connected in series from each other to prevents a leakage current of a substrate and a latch up. A well-bias potential of the PMOS transistor for a conventional high voltage generation circuit is controlled by the two PMOS transistors. By controlling the well-bias potential of the PMOS transistor for a conventional high voltage generation circuit, a leakage current of a substrate due to potential difference of PN layers is prevented.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_TW437065BB |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS SEMICONDUCTOR DEVICES STATIC STORES |
| title | A high voltage generation circuit in a semiconductor device |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-28T00%3A50%3A32IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=KIM,%20MOO-SUK&rft.date=2001-05-28&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ETW437065BB%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |