A high voltage generation circuit in a semiconductor device

A high voltage generation circuit according to the present invention includes two PMOS transistors coupled across a PMOS transistor for a conventional high voltage generation circuit, where the two PMOS transistors being connected in series from each other to prevents a leakage current of a substrate and a latch up. A well-bias potential of the PMOS transistor for a conventional high voltage generation circuit is controlled by the two PMOS transistors. By controlling the well-bias potential of the PMOS transistor for a conventional high voltage generation circuit, a leakage current of a substrate due to potential difference of PN layers is prevented.