Distributed memory reorder buffer in super-scalar pipeline system

The present invention is provided to design a memory reorder buffer in super-scalar pipeline system. This memory reorder buffer is different from the conventional centralized design primarily in using distributed design. The distributed memory reorder buffer of the present invention comprises a storage buffer, a read buffer and a read transfer buffer. The stored instructions are sequentially placed in the storage buffer. The read instructions, that are checked to be entirely the same as the stored instructions in the storage buffer, are placed in the read transfer buffer. The other read instructions are placed in the read buffer. The read instruction that is placed in the read transfer buffer is named as a read transfer instruction. As long as the required data is ready, the read transfer instruction can be issued to the corresponding bus. If the other read instructions are completely unrelated to the previous stored instructions, the read instruction can be issued to the cache at anytime. Otherwise, the read instruction has to wait for being issued after the related stored instructions are issued. The structure of this distributed memory reorder buffer can decrease the complexity of the control circuit and increase the system performance.