Manufacturing method for node contact in the DRAM

The present invention provides a manufacturing method for node contact in the DRAM on a semiconductor chip in which the chip comprises a substrate, a first dielectric on the substrate, a second dielectric on the first dielectric, two strip-type bit lines with nearly rectangular cross-section configured in the second dielectric in parallel, and a photoresist on the second dielectric. The photoresist comprises a hole on top of the gate between the two bit lines. The manufacturing method for the node contact comprises: conducting downwardly a first anisotropic etching along the hole until the node contact is formed primarily on the substrate surface; next, conducting a wet etching to remove the photoresist and the surface layer of the vertical sidewall in the node contact, wherein the removed surface depth on the vertical sidewall of the second dielectric in the node contact is larger than the removed surface depth on the vertical sidewall of the first dielectric; then, forming a passivation on the surface of the second dielectric and the surface of the node contact with dielectric material; then, conducting a second anisotropic etching on the surface of the second dielectric and the node contact to completely remove the passivation located on the surface of the vertical sidewall of the first dielectric and forming a spacer on the passivation on the surface of the vertical sidewall of the second dielectric to prevent the current leakage of the two bit lines.