Power stage bias circuit with improved efficiency and stability

A driver circuit especially for driving scan velocity modulation (SVM) coils or similar loads is characterized by low quiescent current loading and high peak output. The driver is coupled to an input signal varying between a quiescent signal level and a peak signal level. A transistor is coupled to a power supply and to the input signal, so as to conduct according to the input signal. A nonlinear element such as a diode is coupled in series with the emitter-collector junction of the transistor, and is biased to a voltage slightly less than a forward biased conducting diode voltage drop. Thus the diode has a higher resistance when the transistor is conducting at the quiescent signal level, and a lower resistance when the transistor is conducting at the peak signal level. The quiescent bias conditions are maintained by resistors in series and parallel with the diode. The driver may be configured as a complementary push-pull stage.