Current comparator

A current comparator comprises first (1) and second (2) inputs for receiving input currents to be compared. During a first phase (1a) of a clock period the input currents are sensed and stored on first (N1, S7) and second (N2, S8) current memory circuits. On a second phase (1b) of the clock period a switching arrangement (S1 to S4) inverts the input currents and applies them together with the currents stored in the first (N1, S7) and second (N2, S8) current memory circuits to a regenerative latch circuit (P1, P2, S9, S10). During a third phase (2a) of the clock period the comparator produces the comparison result at an output (3). During a fourth phase switches (S5, S6, S9, S10, S11) are operated to reset the comparator to its initial state.