Method for metal etching with reduced sidewall build up during integrated circuit manufacturing

A method in a plasma processing chamber for etching through a selected portion of a layer stack. The layer stack comprises a metallization layer, a first barrier layer disposed adjacent to the metallization layer, and a photoresist layer disposed above the metallization layer. The method includes et...

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Bibliographische Detailangaben
Hauptverfasser: NAEEM,MUNIR D, GREWAL, VIRINDER, BURNS, STUART M, GRECO, NANCY, GRECO, STEVE
Format: Patent
Sprache:eng
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Zusammenfassung:A method in a plasma processing chamber for etching through a selected portion of a layer stack. The layer stack comprises a metallization layer, a first barrier layer disposed adjacent to the metallization layer, and a photoresist layer disposed above the metallization layer. The method includes etching at least partially through the first barrier layer using a high sputter component etch. The method further includes etching at least partially through the metallization layer using a low sputter component etch. The low sputter component etch has a sputter component lower than a sputter component of the high sputter component etch.