Computer processor with dynamic setting of latency values for memory access

A computer processor includes a dynamic latency module. The dynamic latency module includes a read-only memory (""ROM"") in which is stored a plurality of sets of latency values. The dynamic latency module further includes a register coupled to the ROM and adapted to store at least one set of the plurality of sets of latency values. The dynamic latency module dynamically sets a plurality of memory access latency values by determining an operating speed of the processor and implementing one of the plurality of sets of latency values based on the operating speed.