Method for testing and for generating a mapping for an electronic device

A sort of method for testing and generating a mapping for an electronic device, being the logic address to form an indication having a pair of signals and the method having the following steps: (a) setting a relationship between the signal pair and the layout, being the relationship to indicate the...

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Bibliographische Detailangaben
Hauptverfasser:	BRACHA, GABRIEL, WEISBERGER, EYTAN
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS SEMICONDUCTOR DEVICES TESTING
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Beschreibung
Zusammenfassung:	A sort of method for testing and generating a mapping for an electronic device, being the logic address to form an indication having a pair of signals and the method having the following steps: (a) setting a relationship between the signal pair and the layout, being the relationship to indicate the sector of simultaneous occurrence of the signal pair on the layout; (b) setting up a second relationship between the logic address and the signal pair, being the second relationship to indicate the logic address being assigned to the signal pair; and (c) using the key signal pair for merge of the first and the second relationship.