Failure analysis memory for memory testing apparatus

A failure analysis memory for memory testing apparatus which has a failure data storage part composed of a failure data memory and a first memory control part and a mask data storage part composed of a mask data memory and a second memory control part, when the logical comparison result by the testing apparatus is a failure in the test mode, the first memory control part effects control to generate write enable data and write failure data in the failure data memory at the corresponding address and, in the remove mode, effects control to read out failure data from the failure data memory and provide it to the mask data storage, in which in the test mode the second memory control part effects control to provide mask data read out of the mask data memory, as an inhibit signal, to a logic comparator of the memory testing apparatus to inhibit it from making a logical comparison and, in the remove mode, the second memory control part effects control to generate a write enable signal from the failure data read out o