Cached synchronous DRAM architecture allowing concurrent DRAM operations

A cached synchronous dynamic random access memory (cached SDRAM) device having a multi-bank architecture including asynchronous dynamic random access memory (SDRAM) bank including a row decoder coupled to a memory bank array for selecting a row of data in the memory bank array, sense amplifiers coupled to the memory bank array via bit lines for latching the row of data selected by the row decoder, and a synchronous column select means for selecting a desired column of the row of data, a randomly addressable row register storing a row of data latched by the sense amplifiers; select logic gating means, disposed between the sense amplifiers and the row register, selectively gates the row of data present on the bit lines to the row register in accordance to particular synchronous memory operations of the cached SDRAM being performed; data to be input into the cached SDRAM during a Write operation being received by the sense amplifiers and written into the memory bank array; data to be output from the cached SDRAM