Improved memory device performance by delayed power-down

Improved memory device performance by delayed power-down

A method of reducing voltage drop due to chip disable time duration on integrated circuit power bus comprises: (1) Detecting external chip-disable pulses that occur before a minimum time duration; (2) Preventing said chip-disable pulses from powering down selected internal DC path power of integrate...

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Bibliographische Detailangaben
Hauptverfasser: SUNG-WEI LIN, RONALD J. SYZDEK, TIM M. COFFMAN, TIMOTHY J. COOTS, PHAT C. TRUONG
Format: Patent
Sprache:chi ; eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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Beschreibung
Zusammenfassung:A method of reducing voltage drop due to chip disable time duration on integrated circuit power bus comprises: (1) Detecting external chip-disable pulses that occur before a minimum time duration; (2) Preventing said chip-disable pulses from powering down selected internal DC path power of integrated circuit; and (3) At the same time preserving output driver high impedance functionality of chip-disable signal.