A two-line mixed analog/digital bus system and a station for use in such a system

A two-line multi-station bus system has a clock wire and a data wire and supports selective slave station addressing by a prevalent master station for thereupon eliciting a bitwise clocked data transfer between said clocking master station and an addressed and clocked slave station. Moreover, the system supports analog signal transfer in that said prevalent master station has holding means for while eliciting the analog signal from said actual addressed slave station holding said clocking through carrying said clock wire at a predetermined binary value. The analog signal is received until changeover of the clock wire to the other binary value. in a particular version the analog signal is pulse width modulated in combination with associate delimiting signals on the clock wire sent by the transmitter station that is not necessarily the master station.