Branch target buffer access systems and methods

Embodiments of the present disclosure include techniques for branch prediction. A branch predictor may be included in a processor. The branch predictor may use heuristics to control lookups against multiple different memory caches in a branch target buffer. In one embodiment, a branch predictor moni...

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Hauptverfasser:	ARUNACHALAM, SOMASUNDARAM, STREETT, DAREN EUGENE, DOING, RICHARD WILLIAM
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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creator	ARUNACHALAM, SOMASUNDARAM STREETT, DAREN EUGENE DOING, RICHARD WILLIAM
description	Embodiments of the present disclosure include techniques for branch prediction. A branch predictor may be included in a processor. The branch predictor may use heuristics to control lookups against multiple different memory caches in a branch target buffer. In one embodiment, a branch predictor monitors successful lookups and a lookup is performed against one cache before another cache based on a number of successful lookups. In another embodiment, lookups are performed against different caches based on a current available capacity of a fetch target queue.
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subjects	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
title	Branch target buffer access systems and methods
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