Branch target buffer access systems and methods

Embodiments of the present disclosure include techniques for branch prediction. A branch predictor may be included in a processor. The branch predictor may use heuristics to control lookups against multiple different memory caches in a branch target buffer. In one embodiment, a branch predictor monitors successful lookups and a lookup is performed against one cache before another cache based on a number of successful lookups. In another embodiment, lookups are performed against different caches based on a current available capacity of a fetch target queue.