Systems and methods of testing devices using CXL for increased parallelism

Systems and methods of testing devices using CXL for increased parallelism

Embodiments of the present invention can selectively enable 16 lane (x16) or 8 lane (x8) device testing using multiplexor circuitry disposed between a CXL1.1 CPU and the DUTs during testing. In this way, parallelism and testing efficiency are significantly improved compared to existing approaches th...

Ausführliche Beschreibung

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Bibliographische Detailangaben
1. Verfasser: DE LA PUENTE, EDMUNDO
Format: Patent
Sprache:chi ; eng
Schlagworte:
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
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Beschreibung
Zusammenfassung:Embodiments of the present invention can selectively enable 16 lane (x16) or 8 lane (x8) device testing using multiplexor circuitry disposed between a CXL1.1 CPU and the DUTs during testing. In this way, parallelism and testing efficiency are significantly improved compared to existing approaches that can only test devices using 8 lanes of the CXL 1.1 CPU.