Stacked package structure and a manufacturing method thereof

Stacked package structure and a manufacturing method thereof

The present application provides a stacked package structure and a manufacturing method thereof. The stacked package structure includes an upper redistribution layer, a first chip, and an upper molding layer. The first chip is disposed on the upper redistribution layer and is electrically connected...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: CHANGCHIEN, SHANG-YU, HSU, HUNG-HSIN, TSAI, PEIUN, LEE, CHIA-LING
Format: Patent
Sprache:chi ; eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:The present application provides a stacked package structure and a manufacturing method thereof. The stacked package structure includes an upper redistribution layer, a first chip, and an upper molding layer. The first chip is disposed on the upper redistribution layer and is electrically connected to the upper redistribution layer. The upper molding layer is disposed on the first chip and the upper redistribution layer, and is configured to package the first chip. The upper molding layer includes a recess, the recess is recessed relative to a surface of the upper molding layer away from the upper redistribution layer, and the recess is circumferentially formed on a periphery of the upper molding layer.