Interface for a semiconductor chip and semiconductor device with stacked semiconductor chips

An interface for a semiconductor chip provided herein includes bonds. The interface has device layout channels and via layout channels and including a circuitry and routing structure. Each device layout channel is located between two via layout channels in a first direction to form a unit layout channel extending in a second direction intersecting the first direction. The bonds are arranged in a bond map following the via layout channels and outside the device layout channels. Most adjacent two of the bonds in the second direction are arranged in a vertical pitch, two bonds at two opposite sides of the device layout channel in the first direction are arranged in a transversal pitch, and the transversal pitch is greater than the vertical pitch. A portion of the circuitry and routing structure is disposed in the device layout channels. A semiconductor device including stacked semiconductor chips is also provided.