Memory device
In general, according to one embodiment, a memory device includes: a first and a second chip that are in contact with each other on a first surface divided into a first region, a second region surrounding the first region, and a third region surrounding the second region. The first chip includes: a...
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creator | ARAI, SHINYA KAWANISHI, AYAKO |
description | In general, according to one embodiment, a memory device includes: a first and a second chip that are in contact with each other on a first surface divided into a first region, a second region surrounding the first region, and a third region surrounding the second region. The first chip includes: a substrate including a first diffusion region of a first conductivity type and a second diffusion region of a second conductivity type; a first electrode unit including a continuous conductor surrounding the first region; and a second electrode unit surrounding the first region while being spaced from the first electrode unit. The second chip includes: a first interconnect layer; a third electrode unit including a continuous conductor surrounding the first region and being in contact with the first electrode unit; a fourth electrode unit surrounding the first region while being spaced from the third electrode unit and being in contact with the second electrode unit; a first wall unit being in contact with the first |
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The first chip includes: a substrate including a first diffusion region of a first conductivity type and a second diffusion region of a second conductivity type; a first electrode unit including a continuous conductor surrounding the first region; and a second electrode unit surrounding the first region while being spaced from the first electrode unit. The second chip includes: a first interconnect layer; a third electrode unit including a continuous conductor surrounding the first region and being in contact with the first electrode unit; a fourth electrode unit surrounding the first region while being spaced from the third electrode unit and being in contact with the second electrode unit; a first wall unit being in contact with the first</description><language>chi ; eng</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20231001&DB=EPODOC&CC=TW&NR=202339225A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20231001&DB=EPODOC&CC=TW&NR=202339225A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ARAI, SHINYA</creatorcontrib><creatorcontrib>KAWANISHI, AYAKO</creatorcontrib><title>Memory device</title><description>In general, according to one embodiment, a memory device includes: a first and a second chip that are in contact with each other on a first surface divided into a first region, a second region surrounding the first region, and a third region surrounding the second region. The first chip includes: a substrate including a first diffusion region of a first conductivity type and a second diffusion region of a second conductivity type; a first electrode unit including a continuous conductor surrounding the first region; and a second electrode unit surrounding the first region while being spaced from the first electrode unit. The second chip includes: a first interconnect layer; a third electrode unit including a continuous conductor surrounding the first region and being in contact with the first electrode unit; a fourth electrode unit surrounding the first region while being spaced from the third electrode unit and being in contact with the second electrode unit; a first wall unit being in contact with the first</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZOD1Tc3NL6pUSEkty0xO5WFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8SHhRgZGxsaWRkamjsbEqAEAL8seKQ</recordid><startdate>20231001</startdate><enddate>20231001</enddate><creator>ARAI, SHINYA</creator><creator>KAWANISHI, AYAKO</creator><scope>EVB</scope></search><sort><creationdate>20231001</creationdate><title>Memory device</title><author>ARAI, SHINYA ; KAWANISHI, AYAKO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_TW202339225A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2023</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>ARAI, SHINYA</creatorcontrib><creatorcontrib>KAWANISHI, AYAKO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ARAI, SHINYA</au><au>KAWANISHI, AYAKO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Memory device</title><date>2023-10-01</date><risdate>2023</risdate><abstract>In general, according to one embodiment, a memory device includes: a first and a second chip that are in contact with each other on a first surface divided into a first region, a second region surrounding the first region, and a third region surrounding the second region. The first chip includes: a substrate including a first diffusion region of a first conductivity type and a second diffusion region of a second conductivity type; a first electrode unit including a continuous conductor surrounding the first region; and a second electrode unit surrounding the first region while being spaced from the first electrode unit. The second chip includes: a first interconnect layer; a third electrode unit including a continuous conductor surrounding the first region and being in contact with the first electrode unit; a fourth electrode unit surrounding the first region while being spaced from the third electrode unit and being in contact with the second electrode unit; a first wall unit being in contact with the first</abstract><oa>free_for_read</oa></addata></record> |
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language | chi ; eng |
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subjects | INFORMATION STORAGE PHYSICS STATIC STORES |
title | Memory device |
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