Microprocessor and method for processing zero-value data

A microprocessor and method for processing zero-value data are provided. In an embodiment, the microprocessor includes a plurality of cores, each core including a level 1 (L1) cache and a level 2 (L2) cache. The microprocessor also includes a shared level 3 (L3) cache, comprising multiple L3 tag array entries. Wherein a first portion of the plurality of L3 tag array entries is associated with data and a second portion of the plurality of L3 tag array entries is decoupled from data. Wherein each L3 tag array entry includes tag information and data null information indicating whether any data associated with the tag information is known to be zero.