Wafer placement table

Wafer placement table

A wafer placement table 10 includes a ceramic base 20, an electrode (FR attraction electrode 27), a bonding terminal (power supply terminal 82), and an electrode lead-out portion 272. The ceramic base 20 has an upper surface serving as a wafer placement surface 22a. The FR attraction electrode 27 is...

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Hauptverfasser: TAKEBAYASHI, HIROSHI, KOJIMA, MITSURU
Format: Patent
Sprache:chi ; eng
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BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator TAKEBAYASHI, HIROSHI
KOJIMA, MITSURU
description A wafer placement table 10 includes a ceramic base 20, an electrode (FR attraction electrode 27), a bonding terminal (power supply terminal 82), and an electrode lead-out portion 272. The ceramic base 20 has an upper surface serving as a wafer placement surface 22a. The FR attraction electrode 27 is embedded in the ceramic base 20. The power supply terminal 82 is inserted into the ceramic base 20 from a lower surface of the ceramic base 20 and penetrates a through-hole 271 formed in the FR attraction electrode 27. The electrode lead-out portion 272 is provided at each of two or more positions at intervals along a peripheral edge of the through-hole 271 to be thicker than the FR attraction electrode 27 and has an inner peripheral surface 272a bonded to a side surface of the power supply terminal 82.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_TW202329320A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>TW202329320A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_TW202329320A3</originalsourceid><addsrcrecordid>eNrjZBANT0xLLVIoyElMTs1NzStRKElMyknlYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQVAxXmpJfEh4UYGRsZGlsZGBo7GxKgBAGhsIRQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Wafer placement table</title><source>esp@cenet</source><creator>TAKEBAYASHI, HIROSHI ; KOJIMA, MITSURU</creator><creatorcontrib>TAKEBAYASHI, HIROSHI ; KOJIMA, MITSURU</creatorcontrib><description>A wafer placement table 10 includes a ceramic base 20, an electrode (FR attraction electrode 27), a bonding terminal (power supply terminal 82), and an electrode lead-out portion 272. The ceramic base 20 has an upper surface serving as a wafer placement surface 22a. The FR attraction electrode 27 is embedded in the ceramic base 20. The power supply terminal 82 is inserted into the ceramic base 20 from a lower surface of the ceramic base 20 and penetrates a through-hole 271 formed in the FR attraction electrode 27. The electrode lead-out portion 272 is provided at each of two or more positions at intervals along a peripheral edge of the through-hole 271 to be thicker than the FR attraction electrode 27 and has an inner peripheral surface 272a bonded to a side surface of the power supply terminal 82.</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230716&amp;DB=EPODOC&amp;CC=TW&amp;NR=202329320A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25569,76552</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230716&amp;DB=EPODOC&amp;CC=TW&amp;NR=202329320A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>TAKEBAYASHI, HIROSHI</creatorcontrib><creatorcontrib>KOJIMA, MITSURU</creatorcontrib><title>Wafer placement table</title><description>A wafer placement table 10 includes a ceramic base 20, an electrode (FR attraction electrode 27), a bonding terminal (power supply terminal 82), and an electrode lead-out portion 272. The ceramic base 20 has an upper surface serving as a wafer placement surface 22a. The FR attraction electrode 27 is embedded in the ceramic base 20. The power supply terminal 82 is inserted into the ceramic base 20 from a lower surface of the ceramic base 20 and penetrates a through-hole 271 formed in the FR attraction electrode 27. The electrode lead-out portion 272 is provided at each of two or more positions at intervals along a peripheral edge of the through-hole 271 to be thicker than the FR attraction electrode 27 and has an inner peripheral surface 272a bonded to a side surface of the power supply terminal 82.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBANT0xLLVIoyElMTs1NzStRKElMyknlYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQVAxXmpJfEh4UYGRsZGlsZGBo7GxKgBAGhsIRQ</recordid><startdate>20230716</startdate><enddate>20230716</enddate><creator>TAKEBAYASHI, HIROSHI</creator><creator>KOJIMA, MITSURU</creator><scope>EVB</scope></search><sort><creationdate>20230716</creationdate><title>Wafer placement table</title><author>TAKEBAYASHI, HIROSHI ; KOJIMA, MITSURU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_TW202329320A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>TAKEBAYASHI, HIROSHI</creatorcontrib><creatorcontrib>KOJIMA, MITSURU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>TAKEBAYASHI, HIROSHI</au><au>KOJIMA, MITSURU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Wafer placement table</title><date>2023-07-16</date><risdate>2023</risdate><abstract>A wafer placement table 10 includes a ceramic base 20, an electrode (FR attraction electrode 27), a bonding terminal (power supply terminal 82), and an electrode lead-out portion 272. The ceramic base 20 has an upper surface serving as a wafer placement surface 22a. The FR attraction electrode 27 is embedded in the ceramic base 20. The power supply terminal 82 is inserted into the ceramic base 20 from a lower surface of the ceramic base 20 and penetrates a through-hole 271 formed in the FR attraction electrode 27. The electrode lead-out portion 272 is provided at each of two or more positions at intervals along a peripheral edge of the through-hole 271 to be thicker than the FR attraction electrode 27 and has an inner peripheral surface 272a bonded to a side surface of the power supply terminal 82.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Wafer placement table
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-15T17%3A03%3A49IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=TAKEBAYASHI,%20HIROSHI&rft.date=2023-07-16&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ETW202329320A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true