Computer system based on wafer-on-wafer architecture and memory test method

A memory test method for computer systems based on wafer-on-wafer architecture. The computer system is a three-dimensional wafer product formed by a memory wafer layer, a logic circuit layer and a substrate. When a memory test is performed, a memory device in the memory wafer layer is divided into a plurality of memory sub blocks with the same size and tested separately. First, a data table is created in a memory sub block. Then, a plurality of different initial values prepared in advance are provided for a workload proof operation, and the data table is repetitively read and written for plural times to produce multiple operation results corresponding to each initial value. When the verification module obtains operation results from the arithmetic module, the operation results are compares with corresponding known answers, and the error rate of the memory sub block under test is therefore estimated.