Communication latency mitigation for on-chip networks

This application relates to systems and methods for reduced latency in arrays of computing nodes. In some embodiments, a method of routing data can include outputting a first bypass signal and a second bypass signal from a first computing node of an array of computing nodes, wherein the first bypass signal indicates to route packet data through a second computing node and the second bypass signal indicates to turn the packet data in a third computing node. The packet can be routed through the second node based on the first bypass signal in a single clock cycle, and the packet can be routed from the second computing node to the third computing node in a single clock cycle. The second computing node receives the first bypass signal by way of a faster route than it receives the packet data.