Full die and partial die tape outs from common design

Full die and partial die tape outs from common design

A chip design methodology and a set of integrated circuits that are taped out from a common design database are disclosed. The area of a full instance of the integrated circuit is defined, and one or more chop lines are defined to identify portions that will be removed for one or more partial instan...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: BETZALEL, OREN, GITELMAN, LEONID, HAUZI, HAIM, REDSHAW, JONATHAN M, TAMARI, ERAN, HAIM, DALIA R, NISSEL, IDAN, HAMMARLUND, PER H, KOSTIANOVSKY, ALFREDO
Format: Patent
Sprache:chi ; eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:A chip design methodology and a set of integrated circuits that are taped out from a common design database are disclosed. The area of a full instance of the integrated circuit is defined, and one or more chop lines are defined to identify portions that will be removed for one or more partial instances. A variety of techniques and mechanisms are defined to permit the tape outs to occur from a common design database, so that the effort to tape out partial instances may be minimized beyond that to tape out the full instance.